20.05.2022 (15:34:10)
RayeR
:
Jen doplnim:
The DDR3 Design Requirements for Keystone Devices
Address and command signals are routed in a group, length matched to within 10mils, Stubs < 80mil
Clock to Address and Control group within 20mil of the group clock. DiffClk matching to 1mm, clock pair stub < 40mil
DataLine, DQS routing within a group are within 10mil, DQS data differential to within 1mil